The present invention relates to an electronic analog-to-digital converter and more particularly to an analog-to-digital converter which is a charge coupled device.
An analog-to-digital converter is a device which processes, i.e., converts, a continuously variable analog signal to a digital signal, i.e., a binary code, which is a close approximation of the original analog signal. The analog input would be alternating current and the binary code may be of various forms such as serial or parallel.
There have been many different types of analog-to-digital electronic circuits and recently analog-to-digital devices which are based on the use of an integrated circuit have become commercially available. An integrated circuit (IC) is a combination of circuit elements interconnected on a continuous substrate. Frequently the substrate is a base chip (which may be a portion of a wafer) of semiconductive silicon and the circuit may include both active and passive elements contained in a single package.
The analog-to-digital converter of the present invention is a charge coupled device (CCD). A charge coupled device is a semiconductor storage device that employs a charge transfer system in which charges controlled by a gate are contained in capacitors. The entire device may be fabricated on a single crystal wafer to form an integrated circuit. By varying the electrode gate voltages in a programmed succession determined by a logic circuit, a charge packet may be moved from one capacitor to another capacitor and then to an output amplifier. Since the capacitors may contain a controlled and variable charge, the CCD device is a means to store information represented by the charge.
The present invention is particularly directed to a metal oxide semiconductor (MOS) in which the capacitors of the CCD device are formed on the wafer of semiconductive silicon. The type of metal oxide semiconductor device presented as the preferred embodiment of the present invention is a field effect transistor metal oxide semiconductor known as a MOS-FET. In that type of integrated circuit the field effect transistor may be formed with a metal gate electrode isolated (insulated) from a semiconductor channel by an oxide film. A capacitor may be formed, in one method, with the semiconductor material as one plate, aluminum as the other plate, and an oxide between the two plates acting as a dielectric. The MOS-FET may be either an enhancement type, which is normally turned off, or the depletion type, which is normally turned on, although generally, in accordance with the preferred embodiment, the MOS-FET will be of the enhancement type. Generally MOS-FET devices may be formed using diffused source and drain regions on either side of the P or N channel region. When a control voltage is applied to the gate, the channel region is converted to the same type of semiconductor as the source or drain (either P or N), permitting a current path to be established between the source and drain.
Various types of analog-to-digital converters are presently available utilizing integrated circuits. For example, National Semiconductor Corporation has announced an analog-to-digital converter AD1210 which is a 12-bit successive approximation converter, supplied as a 24-pin package. The AD1210 device includes successive approximation logic analog switches, a precision laser trimmed thin film resistor ladder network and a field effect transistor input comparator. According to its published literature, its binary output is directly compatible with CMOS (complementary metal oxide semiconductor) logic levels. A CMOS device has both N and P channel enhancement modes fabricated onto the silicon wafer and generally connected to form push-pull digital complementary circuits. The clock rate of the AD1210 is stated as being up to 500 kHz and its conversion rate is 20 kHz.
A charge coupled device (CCD) analog-to-digital (A/D) device using a MOSFET integrated circuit (IC) is described by Eichelberger & Butler, "An Analog-to-Digital Converter Using Charge-Transfer Technology" in the Digest of Technical Papers, ISSCC77/Thursday, Feb. 17, 1977, Philadelphia, Pa. Sess. 1.X, pages 94,95. In the device described, the number of metered charge packets to fill a well, i.e., fill a capacitor, to a threshold level is linearly related to input d.c. voltage. During an initial period a scale factor is obtained and the number of charge packets to charge a well to a detected threshold value is counted. The implementation described in the article used a P-channel MOS chip of relatively large size (240.times.180 mils). Even using a high clock rate of 500 kHz, the conversion time was relatively slow, 20 ms at 10 bits resolution.